1. Field of the Invention
Embodiments of the invention relate to a semiconductor device and related methods of fabrication. More particularly, embodiments of the invention relate to an image sensor and methods of fabricating the same.
This application claims priority to Korean Patent Application No. 2005-0062436, filed on Jul. 11, 2005, the subject matter of which is hereby incorporated by reference in its entirety.
2. Description of the Related Art
An image sensor is a semiconductor device adapted to convert an optical image into electrical signals. Charge coupled device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors are two types of image sensors. A CMOS image sensor (CIS) comprises a plurality of pixels aligned two-dimensionally (i.e., along rows and columns) and resistance patterns adapted to amplify the signals generated by the pixels.
Each conventional pixel comprises a photodiode, a floating diffusion region, and a transfer transistor. The photodiode is adapted to convert incident light into electrical charge. The transfer transistor is adapted to transfer the charge accumulated in the photodiode to the floating diffusion region. However, when accumulated charge remains in the photodiode, rather than being completely transferred to the floating diffusion region by the transfer transistor, the so-called “after-image” effect arises. The after-image effect results in a deterioration of the image subsequently formed and displayed in relation to the incident light initially received in the CMOS image sensor. Thus, the transfer transistor should be designed and implemented with a sufficiently large drive capacity to completely transfer accumulated charge from the photodiode to the floating diffusion region.
The conventional transfer transistor comprises a transfer gate electrode which is usually formed on a semiconductor substrate from undoped polysilicon. After the transfer gate electrode is formed, n-type impurities (e.g., doping ions) are implanted into the semiconductor substrate to form the floating diffusion region. The transfer gate electrode is concurrently doped with the n-type impurities during implantation into the semiconductor substrate. The resistance patterns are also formed from undoped polysilicon. Like the transfer gate electrode, the resistance patterns are doped when n-type impurities are implanted into the semiconductor substrate to form the floating diffusion region.
FIGS. 1A through 1D are cross-sectional views illustrating one method adapted to the fabrication of a conventional image sensor.
Referring to FIG. 1A, a semiconductor substrate 100 comprising a pixel area A and a resistance area B is prepared. A p-well PW is formed in semiconductor substrate 100, and an isolation layer 105 is formed to define an active region in p-well PW. Resistance area B is covered by isolation layer 105. Agate insulating layer is formed on semiconductor substrate 100 after the isolation layer is formed. Then, a polysilicon layer is formed on semiconductor substrate 100 after the gate insulating layer is formed.
The conventional image sensor also comprises a CMOS device (not shown) formed in a peripheral circuit area. The CMOS device comprises a PMOS area and an NMOS area. A gate electrode of the PMOS area and a gate electrode of the NMOS area, which are each patterned from a polysilicon layer, are doped with p-type impurities and n-type impurities, respectively. This formation technique allows the respective gate electrode elements to be highly integrated while maintaining excellent electrical characteristics. Thus, the polysilicon layer used in this method is formed from an undoped polysilicon layer.
After the polysilicon layer is formed, it is patterned to form a transfer gate electrode TG0 on semiconductor substrate 100 in pixel area A, and a resistance pattern RO on isolation layer 105 in resistance area B. The gate insulating layer is patterned while the polysilicon layer is patterned, thereby forming a transfer gate insulating layer 110 as part of gate electrode TG0. After the polysilicon layer is patterned, a deep n-type impurity region NPD and a shallow p-type impurity region PPD are respectively formed in the active region at a first side of transfer gate electrode TG0 (i.e., a first portion of the active region), thereby forming a photodiode PD, which comprises deep n-type impurity region NPD and shallow p-type impurity region PPD.
Referring to FIGS. 1A and 1B, a first photoresist pattern 120 is formed to cover the upper portion of photodiode PD. First photoresist pattern 120 is formed such that an edge portion 120′ of first photoresist pattern 120 is disposed at an upper central portion of transfer gate electrode TG0. This positioning of the first photoresist pattern 120 minimizes the potential for misalignment errors and provides maximum marginal widths of transfer gate electrode TG0 during subsequent process steps. First impurity ions IP′ are implanted into semiconductor substrate 100 using first photoresist pattern 120 as an ion implantation mask. As a result, a LDD impurity region 125 is formed in the active region at a second side of transfer gate electrode TG0 (i.e., in a second portion of the active region on an opposite side of the transfer gate electrode from the first portion of the active region) and is separated from photodiode PD across at least a portion of transfer gate electrode TG0 disposed between LDD impurity region 125 and photodiode PD. Also, a region TG1 doped with first impurity ions IP′ is formed in the portion of transfer gate electrode TG0 exposed outside of first photoresist pattern 120. In addition, resistance pattern R1, as doped with first impurity ions IP′, is formed on semiconductor substrate 100 in resistance area B. First impurity ions IP′ are typically n-type.
Referring to FIG. 1C, second impurity ions IP″ are implanted into semiconductor substrate 100 by a tilt ion implantation method using first photoresist pattern 120 as an ion implantation mask. As a result, a shallow impurity region 130 is formed in the second portion of the active region and is separated from photodiode PD across at least a portion of transfer gate electrode TG0. This portion of transfer gate electrode TG0 includes at least the exposed region TG2 disposed between shallow impurity region 130 and photodiode PD which has been successively doped by first and second impurity ions IP′ and IP″. Resistance pattern R2 is also doped with first and second impurity ions IP′ and IP″. Second impurity ions IP″ are typically p-type.
Referring to FIGS. 1C and 1D, first photoresist pattern 120 is removed and spacers 135 are formed to cover the sidewalls of transfer gate electrode TG0, and resistance pattern R2. After forming spacers 135, a second photoresist pattern 140 having the same pattern as that of first photoresist pattern 120 is formed on semiconductor substrate 100. An edge portion 140′ of second photoresist pattern 140, like edge portion 120′ of first photoresist pattern 120, is disposed at the upper central portion of transfer gate electrode TG0/TG2.
Then, third impurity ions IP′″ are implanted into semiconductor substrate 100 using second photoresist pattern 140 as an ion implantation mask. As a result, an n-type impurity region 145 is formed in the second portion of the active region and is separated from photodiode PD across transfer gate electrode TG0/TG3, where region TG3 of the transfer gate electrode has been successively doped with first, second, and third impurity ions IP′, IP″, and IP′″. In addition, a resistance pattern R3 doped with first, second, and third impurity ions IP′, IP″, and IP′″ is formed in resistance area B. Third impurity ions IP′″ are typically n-type impurity ions having a higher concentration density than that used in the first implantation of impurity ions IP′. N-type LDD impurity region 125, and n+-type impurity region 145 constitute a floating diffusion region FD. Deep n-type impurity region NPD of photodiode PD, transfer gate electrode TG0/TG3, and floating diffusion region FD constitute a transfer transistor.
Since edge portion 140′ of second photoresist pattern 140 is disposed at the upper central portion of transfer gate electrode TG0/TG3, the portion of transfer gate electrode TG0/TG3 covered by second photoresist pattern 140 (i.e., transfer gate electrode region TG0) remains undoped polysilicon. Thus, the driving capacity of the transfer transistor may be limited, because the undoped polysilicon portion of transfer gate electrode TG0 tends to reduce the electrical responsiveness of transfer gate electrode TG0/TG3.
It is true that second photoresist pattern 140 may be formed to expose the entire upper portion of transfer gate electrode TG0 in order to prevent this problem, but photoresist pattern misalignment problems may be generated. Consider, for example, the misalignment of photoresist pattern 140 shown by the alternate edge 140″ shown in FIG. 1D. Such a misalignment, results in a small portion of photodiode PD being doped by third impurity ions IP′″. As a result, an n+-type tip region nT is formed within photodiode PD. Since n+-type tip region nT comprises many stray electrons, these electrons will migrate into deep n-type impurity region NPD of photodiode PD. Thus, noise will be generated in photodiode PD due to increased dark level effects. That is, dark level effects increase because of the stray electrons provided by n+-type tip region nT. Such dark level effects distort the sensitivity threshold of the photodiode PD.
A conventional method of fabricating an image sensor is disclosed, for example, in published U.S. Patent Application No. 2003/0173585 A1. In this disclosure, a transfer gate electrode is formed to intersect with an active region, and a first photoresist pattern is formed to expose a first end portion of the transfer gate electrode and a first portion of the active region adjacent to the first end portion of the transfer gate. Then, using the first photoresist pattern as an ion implantation mask, n-type and p-type impurities are sequentially implanted into the first portion of the active region, wherein the p-type impurities are implanted with a higher concentration than the n-type impurities, thereby forming a deep n-type impurity region and a shallow p-type impurity region of a photodiode. In this case, the transfer gate electrode exposed by the first photoresist pattern is doped with p-type impurities.
Then, the first photoresist pattern is removed, and a second photoresist pattern that does not cover a second portion of the active region is formed. The second portion of the active region is separated from the photodiode across at least some portion of the transfer gate electrode. Also, a second end portion of the transfer gate electrode is adjacent to the second portion of the active region. Then, using the second photoresist pattern as an ion implantation mask, n-type impurities are implanted into the second portion of the active region, thereby forming a floating diffusion region. At this time, the exposed transfer gate electrode is also doped with n-type impurities. However, the respective portions of the transfer gate electrode exposed by the second photoresist pattern may be changed due to photoresist pattern misalignment problems. That is, since the various doped regions of a transfer gate electrode may be changed by misalignment errors, the electrical characteristics of the electrode depart from design specifications. Further, since one portion of a transfer gate electrode exposed by a first photoresist pattern may be doped with p-type impurities, a p-n junction may actually be formed within the transfer gate electrode itself. This result will clearly lead to deterioration in the electrical characteristics of the transfer gate electrode.